from the Romania-Oriented-Presentations dept.
is now over, and slides for OpenBSD-related presentations are now available
As always, there's some great reading there (especially for those of us
who were unable to attend the conference).
Unfortunately, there will not be any video this year.
Carlos Cardenas (ccardenas@) added support for
image support to vmd(8).
[This builds on an
adding support for pluggable disk backends.]
The code was written by Ori Bernstein, who posted his diffs (thread 1, thread 2) to the firstname.lastname@example.org mailing list in August.
from the all-your-benchmarks-are-belong-to-us dept.
message to tech@,
Theo de Raadt (deraadt@)
gives an update on the state-of-play regarding processor vulnerabilities:
Two recently disclosed hardware bugs affected Intel cpus:
- T1TF (the name "Foreshadow" refers to 1 of 3 aspects of this
bug, more aspects are surely on the way)
Solving these bugs requires new cpu microcode, a coding workaround,
*AND* the disabling of SMT / Hyperthreading.
Theo de Raadt (deraadt@) has
a diff to mitigate the
"Intel L1TF screwup" for the amd64 platform we reported on earlier:
From: Theo de Raadt (elided)
Date: Tue, 21 Aug 2018 13:04:41 -0600 (MDT)
Subject: CVS: cvs.openbsd.org: src
Module name: src
Changes by: email@example.com 2018/08/21 13:04:41
sys/arch/amd64/amd64: identcpu.c vmm.c vmm_support.S
sys/arch/amd64/include: cpu.h specialreg.h vmmvar.h
Perform mitigations for Intel L1TF screwup. There are three options:
(1) Future cpus which don't have the bug, (2) cpu's with microcode
containing a L1D flush operation, (3) stuffing the L1D cache with fresh
data and expiring old content. This stuffing loop is complicated and
interesting, no details on the mitigation have been released by Intel so
Mike and I studied other systems for inspiration. Replacement algorithm
for the L1D is described in the tlbleed paper. We use a 64K PA-linear
region filled with trapsleds (in case there is L1D->L1I data movement).
The TLBs covering the region are loaded first, because TLB loading
apparently flows through the D cache. Before performing vmlaunch or
vmresume, the cachelines covering the guest registers are also flushed.
with mlarkin, additional testing by pd, handy comments from the
kettenis and guenther peanuts
Theo de Raadt (deraadt@)
posted to the tech@ mailing list with some background on how the latest discovered Intel CPU
issues relate to OpenBSD.
Date: Wed, 15 Aug 2018 00:31:16 -0600
From: Theo de Raadt [elided]
Subject: CVE-2018-3615, CVE-2018-3620, CVE-2018-3646
These 3 issues all relate to a bug in Intel cpus
The cpu will speculatively honour invalid PTE against data in the
on-core L1 cache. Memory disclosure occurs into the wrong context.
These 3 issues (CVE-2018-3615, CVE-2018-3620, CVE-2018-3646) together
are the currently public artifacts of this one bug.